Hardware architecture: Peripheral Processors

Each PP had 4096 words of 12 bits memory (see photo). This PP memory was equivalent to one (1) core memory block. Later 800-series systems had 8K words of 16 bit SECDED memory. The limited instruction set allowed internal processing, read/write to Central Memory, read/write to I/O channels and exchanging the CPU.
There was only one accumulator and there were direct cells (like in the PDP8) that allowed efficient and compact 12 bit instructions.

PP's were organized in groups of 10 (in the 800-series systems in groups of 5) or barrels. As said before, each PP was perceived as a single, separate processor in the system. In reality, only one hardware processor serviced a complete barrel of PP's. Using shift-registers, PP instructions were processed in either one, two or 5 minor (memory read/write) cycles. For the CYBER 840 system that meant that each PP register moved through the barrel at a 20 MHz rate, causing each PP tio run at 4 MHz.
Each PP barrel had a:

• R(elocate) register   (22 bits; 800 series only) forms, in conjunction with the A-register the absolute address for a CM read/write in the virtual state. When bit 17 of A is set, the R-register was extended with 6 zero bits at the lower (right) end before the contents of the A-register is added. Otherwise, only the A-register is used (6000/170-state). (A)
• A(ddress) and Accumulator register   (18 bits)
• P(rogram counter)   (12 bits; 16 bits in the 800-series), contains the PP program address. The exceptions are the 61, 63, 71 and 73 instructions where P contains the PP memory address of the transfer. A deadstart, P is set to zero.
• Q register  (12 bits; 16 bits in the 800-series): operand register during (in)direct addressing, the data pointer during CM-read/write, channel number, shift count and so on.
• K register  (7 bits): operations code.
• 5-stage CM word read pyramid (60 bits 6000/70-series or 64 bits 800-series)
• 5-stage CM word write pyramid (60 bits 6000/70-series or 64 bits 800-series)

At a deadstart, all PP's were forced to do a loop for input available on their "own" channel. As the first bytes from the deadstart panel were forced into PP0, PP0 (MTR) was responsible to output the Standard Library (STL) to each PP on its own channel during the start-up phase of the system. Deadstarts could be initiated by using a hardware button between the two console "eyes" or under the single console screen in later systems. Another way was using the deadstart switch adjacent to the deadstart panel. After some time, system programmers and operators were very experienced in "toggling in" the deadstart program in the 16 or 20 rows with switches. It was always amazing that one could (warm)start from a deadstart tape (later a disk) using only 7 to 12 PP words located in the deadstart panel.

       01 1402        LDN  2         load 2
       02 73ch        OAM  out,ch    output 2 words from 17B on ch
       03 0017
       04 754ch       DCN  ch        disconnect channel ch
       05 77ch        FNC  120B,ch   function 120B on ch
       06 0120
       07 74ch        ACN  ch        activate ch
       10 71ch        IAM  7301B,ch  read (A) words from ch to 7301
       11 7301
       12 0710        MJN  hang

       17 0000   out  0000
       20 7112        7112
       21 0000   hang